-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "12/05/2021 17:25:40"

-- 
-- Device: Altera EP4CGX15BF14C6 Package FBGA169
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIV;
LIBRARY IEEE;
USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	mux IS
    PORT (
	a : IN std_logic_vector(2 DOWNTO 0);
	b : IN std_logic_vector(2 DOWNTO 0);
	x : OUT std_logic_vector(5 DOWNTO 0)
	);
END mux;

-- Design Ports Information
-- x[0]	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- x[1]	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- x[2]	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- x[3]	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- x[4]	=>  Location: PIN_M9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- x[5]	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a[0]	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b[0]	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a[1]	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b[1]	=>  Location: PIN_N11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a[2]	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b[2]	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF mux IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_a : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_b : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_x : std_logic_vector(5 DOWNTO 0);
SIGNAL \x[0]~output_o\ : std_logic;
SIGNAL \x[1]~output_o\ : std_logic;
SIGNAL \x[2]~output_o\ : std_logic;
SIGNAL \x[3]~output_o\ : std_logic;
SIGNAL \x[4]~output_o\ : std_logic;
SIGNAL \x[5]~output_o\ : std_logic;
SIGNAL \b[0]~input_o\ : std_logic;
SIGNAL \a[0]~input_o\ : std_logic;
SIGNAL \my1|aband~combout\ : std_logic;
SIGNAL \b[1]~input_o\ : std_logic;
SIGNAL \a[1]~input_o\ : std_logic;
SIGNAL \ad2|sum~0_combout\ : std_logic;
SIGNAL \ad2|cout~0_combout\ : std_logic;
SIGNAL \a[2]~input_o\ : std_logic;
SIGNAL \my3|aband~combout\ : std_logic;
SIGNAL \ad3|sum~combout\ : std_logic;
SIGNAL \b[2]~input_o\ : std_logic;
SIGNAL \a3|sum~0_combout\ : std_logic;
SIGNAL \ad3|cout~0_combout\ : std_logic;
SIGNAL \ad4|sum~combout\ : std_logic;
SIGNAL \a3|cout~0_combout\ : std_logic;
SIGNAL \a4|sum~combout\ : std_logic;
SIGNAL \a4|cout~0_combout\ : std_logic;
SIGNAL \ad4|cout~0_combout\ : std_logic;
SIGNAL \a5|sum~combout\ : std_logic;
SIGNAL \a5|cout~0_combout\ : std_logic;

BEGIN

ww_a <= a;
ww_b <= b;
x <= ww_x;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

-- Location: IOOBUF_X20_Y0_N2
\x[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \my1|aband~combout\,
	devoe => ww_devoe,
	o => \x[0]~output_o\);

-- Location: IOOBUF_X24_Y0_N9
\x[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ad2|sum~0_combout\,
	devoe => ww_devoe,
	o => \x[1]~output_o\);

-- Location: IOOBUF_X33_Y11_N9
\x[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \a3|sum~0_combout\,
	devoe => ww_devoe,
	o => \x[2]~output_o\);

-- Location: IOOBUF_X29_Y0_N2
\x[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \a4|sum~combout\,
	devoe => ww_devoe,
	o => \x[3]~output_o\);

-- Location: IOOBUF_X24_Y0_N2
\x[4]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \a5|sum~combout\,
	devoe => ww_devoe,
	o => \x[4]~output_o\);

-- Location: IOOBUF_X20_Y0_N9
\x[5]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \a5|cout~0_combout\,
	devoe => ww_devoe,
	o => \x[5]~output_o\);

-- Location: IOIBUF_X31_Y0_N8
\b[0]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b(0),
	o => \b[0]~input_o\);

-- Location: IOIBUF_X33_Y10_N8
\a[0]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a(0),
	o => \a[0]~input_o\);

-- Location: LCCOMB_X25_Y1_N8
\my1|aband\ : cycloneiv_lcell_comb
-- Equation(s):
-- \my1|aband~combout\ = (\b[0]~input_o\ & \a[0]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \b[0]~input_o\,
	datad => \a[0]~input_o\,
	combout => \my1|aband~combout\);

-- Location: IOIBUF_X26_Y0_N1
\b[1]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b(1),
	o => \b[1]~input_o\);

-- Location: IOIBUF_X22_Y0_N8
\a[1]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a(1),
	o => \a[1]~input_o\);

-- Location: LCCOMB_X25_Y1_N10
\ad2|sum~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ad2|sum~0_combout\ = (\b[1]~input_o\ & (\a[0]~input_o\ $ (((\b[0]~input_o\ & \a[1]~input_o\))))) # (!\b[1]~input_o\ & (\b[0]~input_o\ & (\a[1]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110101011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[1]~input_o\,
	datab => \b[0]~input_o\,
	datac => \a[1]~input_o\,
	datad => \a[0]~input_o\,
	combout => \ad2|sum~0_combout\);

-- Location: LCCOMB_X25_Y1_N6
\ad2|cout~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ad2|cout~0_combout\ = (\b[1]~input_o\ & (\b[0]~input_o\ & (\a[1]~input_o\ & \a[0]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[1]~input_o\,
	datab => \b[0]~input_o\,
	datac => \a[1]~input_o\,
	datad => \a[0]~input_o\,
	combout => \ad2|cout~0_combout\);

-- Location: IOIBUF_X26_Y0_N8
\a[2]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a(2),
	o => \a[2]~input_o\);

-- Location: LCCOMB_X25_Y1_N28
\my3|aband\ : cycloneiv_lcell_comb
-- Equation(s):
-- \my3|aband~combout\ = (\a[2]~input_o\ & \b[0]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \a[2]~input_o\,
	datad => \b[0]~input_o\,
	combout => \my3|aband~combout\);

-- Location: LCCOMB_X25_Y1_N0
\ad3|sum\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ad3|sum~combout\ = \ad2|cout~0_combout\ $ (\my3|aband~combout\ $ (((\a[1]~input_o\ & \b[1]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011001100110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ad2|cout~0_combout\,
	datab => \my3|aband~combout\,
	datac => \a[1]~input_o\,
	datad => \b[1]~input_o\,
	combout => \ad3|sum~combout\);

-- Location: IOIBUF_X29_Y0_N8
\b[2]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b(2),
	o => \b[2]~input_o\);

-- Location: LCCOMB_X25_Y1_N2
\a3|sum~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \a3|sum~0_combout\ = \ad3|sum~combout\ $ (((\b[2]~input_o\ & \a[0]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \ad3|sum~combout\,
	datac => \b[2]~input_o\,
	datad => \a[0]~input_o\,
	combout => \a3|sum~0_combout\);

-- Location: LCCOMB_X25_Y1_N12
\ad3|cout~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ad3|cout~0_combout\ = (\ad2|cout~0_combout\ & ((\my3|aband~combout\) # ((\a[1]~input_o\ & \b[1]~input_o\)))) # (!\ad2|cout~0_combout\ & (\my3|aband~combout\ & (\a[1]~input_o\ & \b[1]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ad2|cout~0_combout\,
	datab => \my3|aband~combout\,
	datac => \a[1]~input_o\,
	datad => \b[1]~input_o\,
	combout => \ad3|cout~0_combout\);

-- Location: LCCOMB_X25_Y1_N30
\ad4|sum\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ad4|sum~combout\ = \ad3|cout~0_combout\ $ (((\b[1]~input_o\ & \a[2]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[1]~input_o\,
	datac => \ad3|cout~0_combout\,
	datad => \a[2]~input_o\,
	combout => \ad4|sum~combout\);

-- Location: LCCOMB_X25_Y1_N16
\a3|cout~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \a3|cout~0_combout\ = (\ad3|sum~combout\ & (\b[2]~input_o\ & \a[0]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \ad3|sum~combout\,
	datac => \b[2]~input_o\,
	datad => \a[0]~input_o\,
	combout => \a3|cout~0_combout\);

-- Location: LCCOMB_X25_Y1_N18
\a4|sum\ : cycloneiv_lcell_comb
-- Equation(s):
-- \a4|sum~combout\ = \ad4|sum~combout\ $ (\a3|cout~0_combout\ $ (((\a[1]~input_o\ & \b[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011001100110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ad4|sum~combout\,
	datab => \a3|cout~0_combout\,
	datac => \a[1]~input_o\,
	datad => \b[2]~input_o\,
	combout => \a4|sum~combout\);

-- Location: LCCOMB_X25_Y1_N20
\a4|cout~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \a4|cout~0_combout\ = (\ad4|sum~combout\ & ((\a3|cout~0_combout\) # ((\a[1]~input_o\ & \b[2]~input_o\)))) # (!\ad4|sum~combout\ & (\a3|cout~0_combout\ & (\a[1]~input_o\ & \b[2]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ad4|sum~combout\,
	datab => \a3|cout~0_combout\,
	datac => \a[1]~input_o\,
	datad => \b[2]~input_o\,
	combout => \a4|cout~0_combout\);

-- Location: LCCOMB_X25_Y1_N22
\ad4|cout~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ad4|cout~0_combout\ = (\b[1]~input_o\ & (\ad3|cout~0_combout\ & \a[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b[1]~input_o\,
	datac => \ad3|cout~0_combout\,
	datad => \a[2]~input_o\,
	combout => \ad4|cout~0_combout\);

-- Location: LCCOMB_X25_Y1_N24
\a5|sum\ : cycloneiv_lcell_comb
-- Equation(s):
-- \a5|sum~combout\ = \a4|cout~0_combout\ $ (\ad4|cout~0_combout\ $ (((\a[2]~input_o\ & \b[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \a[2]~input_o\,
	datab => \a4|cout~0_combout\,
	datac => \ad4|cout~0_combout\,
	datad => \b[2]~input_o\,
	combout => \a5|sum~combout\);

-- Location: LCCOMB_X25_Y1_N26
\a5|cout~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \a5|cout~0_combout\ = (\a4|cout~0_combout\ & ((\ad4|cout~0_combout\) # ((\a[2]~input_o\ & \b[2]~input_o\)))) # (!\a4|cout~0_combout\ & (\a[2]~input_o\ & (\ad4|cout~0_combout\ & \b[2]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110100011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \a[2]~input_o\,
	datab => \a4|cout~0_combout\,
	datac => \ad4|cout~0_combout\,
	datad => \b[2]~input_o\,
	combout => \a5|cout~0_combout\);

ww_x(0) <= \x[0]~output_o\;

ww_x(1) <= \x[1]~output_o\;

ww_x(2) <= \x[2]~output_o\;

ww_x(3) <= \x[3]~output_o\;

ww_x(4) <= \x[4]~output_o\;

ww_x(5) <= \x[5]~output_o\;
END structure;


